1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically, to a sense operation of a DRAM.
2. Description of Related Art
In recent years, in a semiconductor device used in a communication device or a high-end computer, low power consumption or high-speed access has been required.
Along with the low power consumption or the high-speed operation, highly enhanced performance has been required in the DRAM. More specifically, a power supply voltage input to the DRAM has been reducing.
FIG. 7 shows waveforms showing an operation of a typical DRAM. Although the detailed description is omitted, sensing is performed by raising a sense amplifier activating signal SAE with a word line W being raised. A bit line pair D and DB, which has been precharged to an intermediate potential ½ VCC between a power supply voltage VCC and a ground voltage GND before starting the sensing, is set to a true complement differential potential (ΔV in FIG. 7) in accordance with the cell state. Then the bit line pair D and DB is amplified to the power supply voltage and the ground voltage, respectively. FIG. 7 shows a sensing in which information of a cell (also referred to as cell H) storing “1” is amplified to the bit line D side.
The reduced voltage described above means that the differential potential between VCC and GND in FIG. 7 decreases. In other words, the amplitude of the bit line pair D and DB decreases. Therefore, a charge amount determining the cell state described above also decreases as the amplitude potential decreases.
It is also expected in the DRAM to not only reduce voltage but also reduce power consumption. In order to attain these objects, it is desired to extend a cycle of refreshing storage elements, which is one factor of determining the power consumed by the DRAM. To be more specific, it is desired to improve the degradation of hold characteristics along with the miniaturization of the DRAM device.
Generally, in a cell employing an Nch transistor, the hold characteristics of the DRAM cell is determined by the fact that the charge of the cell storing “1” is drawn out, which means that the differential potential ΔV shown in FIG. 7 is made smaller. Finally, when the sense amplifier cannot determine that the potential difference described above is higher with respect to ½ VCC, then the false sense is generated and the cell is determined as hold failure.
The above description assumes that the DRAM cell is formed by the Nch transistor and a capacitor; however the DRAM cell may be formed by a Pch transistor and a capacitor.
Further, the high-speed operation of the DRAM device has been expected within a limit of low voltage and low power consumption.
A technique of increasing the speed of the DRAM device with low voltage is disclosed in the following patent document, for example.
Japanese Unexamined Patent Application Publication No. 2004-220753 (Ueda) discloses a technique of applying the potential below the ground to a low potential side of the power supply voltage of the sense amplifier for only a brief period of time for the purpose of increasing the sensing speed of the sense amplifier.
However, in the related art, improvement of the hold characteristics of the DRAM cell has not been considered. Therefore, decrease of the power consumption has not been considered.
Therefore, in Ueda, the precharge voltage of the sense amplifier is set to ½ VCC, which is half the power supply voltage VCC. In this case, when the charge amount held in the cell decreases as the voltage decreases, the hold time of the cell is extremely reduced.
As a result, refresh interval performed on the DRAM cell needs to be made shorter in order to ensure the hold characteristics of the DRAM cell, which increases the power consumption.